1. Field of Invention
The present invention relates to semiconductor devices and more particularly to a compact layout for a semiconductor device.
2. Description of Related Art
Typically in the design of a power amplifier, a number of transistor elements are arranged in rows and columns and then connected to provide a large equivalent power device. For example, FIG. 11 shows a conventional layout design for a semiconductor device 132 where a number of BJTs (Bipolar Junction Transistors) 134 are arranged in rows on the upper surface of a semiconductor substrate. Each BJT 134 includes an emitter contact 136, a base contact 138, and a collector contact 140. The emitter contacts 136 are connected by metal 142 to an electrode 144 that lies between the rows of BJTs 134, and the electrode 144 lies above vias 146 that provide an electrical connection to ground. The use of vias for electrical connections is well known in the art of semiconductor devices. (“Semiconductor Device Including Via Hole and Isolating Circumferential Member”, U.S. Pat. No. 5,917,209.)
FIG. 12 shows a cross section of the semiconductor substrate through one of the vias 146. The via 146 is defined by a via inner wall 148 in the substrate 150. The upper surface electrode 144 is electrically connected to a lower surface electrode 152 by means of the via inner wall 148, and the lower surface electrode 152 is electrically connected to a ground plane 154. Then each BJT emitter is electrically connected to the ground plane 154.
For the design shown in FIG. 11 to function as a single power amplifier, the bases and the collectors are electrically connected. FIGS. 13A, 13B, and 13C illustrate three ways that these connections can be made for the emitters, bases and electrodes in an amplifier design. When all emitter contacts for example are connected to an upper electrode as shown in FIG. 11, then a via can be used to make an electrical connection to a lower electrode as shown in FIG. 12. Similarly FIG. 13A shows a via defined by a via inner 156 wall that connects an upper electrode 158 on a semiconductor substrate 160 with a lower electrode 162. Alternatively in the above example where the emitter contacts are connected to an upper electrode, a connection to a lower electrode can be made by a wire or metal layer. In FIG. 13B an upper electrode 164 on a semiconductor substrate 166 is connected to a lower electrode 168 by means of a wire 170 that is separated from the substrate 166 by an insulator 172.
In FIGS. 13A and 13B, the lower electrode can be driven by a single voltage source. In designs without electrodes, wires from a common voltage source can be connected to the connectors that are being driven together. FIG. 13C shows a tree-structure design for inputs to the collectors in a row of eight BJTs 174 on a semiconductor substrate surface 176. A wire 178 with a tree structure connects a collector feed 180 to collector contacts 182. Since the wire path-length from the collector feed 180 to each BJT 174 is the same, difficulties associated with different path-lengths may be avoided. For example, different path-lengths may lead to differences in DC drops, in inductances, and in heat conduction in the elements of the power amplifier.
However, even when differences between elements of a power amplifier are minimized, layout and device geometries may seriously affect the maximum achievable performance of the amplifier. For example, the inductance in the paths from emitters to the ground plane may substantially affect performance of an amplifier, whether these paths are uniform or not. Additionally these paths also affect the quality of heat conduction in the device. Moreover, although examples presented here employ BJTs, similar considerations apply for designs involving other transistor elements such as FETs (Field Effect Transistors).